Development of a working integrated circuit chip is a process that involves creating a design specification, creating the logical design of the chip (typically in schematic form), validating the design, re-designing as necessary, fabricating the chip and testing the chip. Costs tend to be "end-loaded," i.e., greater towards the end of the process than towards the beginning. The earlier in this process that a design error is detected, the earlier it can be corrected, saving a great deal of cost over a late-detected error. As a result, increasingly sophisticated steps are being taken to validate the design of a new chip, as early in the design process as possible.
Design validation requires thorough examination of the integrated circuit design and expected functional characteristics, taking into account a number of different factors, such as logical correctness of the design, timing factors (including net delay performance, power dissipation, effects of parasitic capacitances, etc.) Among these factors, net performance (specifically, net delay) is one of the most important. Many timing-related problems have been discovered in chips whose designs appear to be "logically" correct, at least on paper. This is because it is difficult for the designer to anticipate such delay contributors as wiring delays (net delays) and the cumulative effects of distributed resistances and capacitances on the chips, especially from a post-layout point of view. The accuracy of delay determination affects not only the chip performance, but whether a chip meets its original design specification.
Virtually all integrated circuit designers today use semiconductor design automation systems which facilitate the capture, simulation, layout, and verification of integrated circuit designs. With the advance of semiconductor process technology, integrated circuits are becoming increasingly fast, and the relatively small delays caused by interconnections (wiring) on a chip are becoming a more dominant factor in integrated circuit performance. As a result, the ability to accurately model and calculate wiring delays (net delays) is becoming a crucial requirement for any semiconductor design automation system. These small wiring delays (i.e., the time required for a critical threshold voltage at a receiving node to be crossed after the application of a driving signal at a driving node) are known as "net delays".
One of the by-products of an integrated circuit design on a semiconductor design automation system is a "net-list" which contains a complete description of all of the devices (e.g., transistors, resistors, etc.) required, and how they are connected. The connections are described in the form of "nets" (short for "networks") or descriptions of the point-to-point wiring connections between components. A single net may connect to many components. Any chip design will have a great number of nets. The net-list includes a list of net interconnections, thus the name "net-list".
From any driving point to any receiving point on a net, there is an associated delay. This time is due to a complicated combination of parasitic capacitances, wiring resistances, wire lengths, etc.. Some nets have multiple drivers (e.g., a number of open-drain or tri-state drivers), or loops (e.g., clock rings) making their (accurate) analysis particularly complicated. The delay for a net is determined by modeling the net and analyzing the delay according to the model. One of the most serious problems in delay calculation (determination) is that accurate models tend to complicate delay calculations, resulting in very long delays in the design cycle while computation-intensive net delays are being calculated. As a result, most prior-art net delay calculation techniques compromise on the accuracy (faithfulness to reality) of the model of the net in order to decrease the amount of calculation time required. Unfortunately, in doing so most such techniques sacrifice enough accuracy that the results of delay calculation are only very rough approximations of actual chip performance. As a result, many chips, particularly those with complicated timing relationships between signals, have subtle timing-related problems when they are built. The designs of such chips must then be altered, re-simulated, etc., and a new chip must be fabricated. This process is extremely costly.
In the prior art, techniques such as the modified upper-lower bound method are used to calculate interconnect delay. The upper-lower bound method is described in J. Rubenstein, P. Penfield, and M. A. Horowitz, "Signal Delay in RC Tree Networks," IEEE Trans. Computer-Aided Design, vol CAD-2, pp 202-211, 1983. This method computes adequate results for many nets, and is efficient in computing time. For some large nets, multiple-driver nets, and nets with loops (i.e., clock rings), however, it does not perform well, providing delay estimations which differ significantly from reality. In such cases, more accurate and sophisticated computational methods are required to achieve the necessary accuracy. However, the conventional SPICE method to achieve accurate results takes enormous computation time and is impractical to incorporate into a semiconductor design automation system. (SPICE is the name of a commonly-used analog circuit simulation technique for digital computers).
In 1990, L. Pillage and R. Rohrer from CMU proposed a new method called "Asymptotic Waveform Evaluation", hereinafter "AWE", which is based on the frequency domain analysis, to simulate the waveform response of a circuit (see L. Pillage and R. Rohrer, "Asymptotic Waveform Analysis for Timing Analysis," IEEE Trans. Computer-Aided Design, April, 1990, appended hereto). The AWE method is an iterative "state-transition matrix" technique, that is, it makes use of a vector-matrix multiplication technique to determine voltages at various points along a net in discrete-time fashion. Iterative matrix multiplication techniques are well known to those of ordinary skill in the art. Crucial to the AWE method is the efficient determination of "moments", which are used to create the matrix coefficients. The AWE method is 1000 to 100,000 times faster than SPICE (when compared on the same digital computer) and for nets without loops (i.e., RC-tree), it can achieve very accurate results. However, it is not suited to generalized RC-mesh problems, because it cannot handle loops. Since the interconnect portion of an integrated circuit chip design is essentially a generalized RC-mesh circuit, and some signals on an integrated circuit (e.g., a clock distribution network) contain loops, the AWE method, is not well suited to general-purpose delay determination in semiconductor design automation systems.